The present invention relates generally to complementary metal oxide semiconductor ("CMOS") gate array structures. More particularly, the invention relates to a base cell design for use in such gate array structures.
A gate array is a type of integrated circuit ("IC") made from an array of repeating identical base cells in a core region of a semiconductor chip. Each such base cell contains the same predetermined number and arrangement of MOS transistors. And, as in all MOS-based ICs, each such transistor includes two source/drain diffusion regions separated by a channel region in a silicon substrate, together with a gate located over the channel region. Each gate includes a thin layer of gate oxide sandwiched between a polysilicon gate electrode and the channel region of the substrate.
A gate array masterslice structure contains no prespecified circuitry, only unwired MOS transistors which will later be wired to one another to form circuit elements. Thus, a transistor level gate array structure provides the flexibility to form many different types of integrated circuits--such as for example memory chips and logic chips. The ultimate design of such gate array integrated circuits is determined by the back-end processing employed (i.e., the processing to form and pattern metallization layers and thereby create wiring between the many transistors available on the underlying base cells). It is the arrangement of these interconnections that defines the circuitry present on a given gate array integrated circuit. Because of their versatility, gate arrays are widely used to make application specific integrated circuits (ASICs).
FIG. 1a shows a basic gate array structure 10 provided on a semiconductor die 23 and including a core region 24 containing an array of identical base cells such as base cell 20. As shown, the base cells are generally rectangular and are arranged in repeating rows and columns. Within each base cell, a collection of transistors (not shown) is provided. In each column of base cells within the core region 24, a first metal line 21 and another first metal line 22 span the length of the core region. Metal line 22 is used to deliver power (Vdd) to individual base cells in the column of the array, while metal line 21 provides ground (Vss) to each base cell in the column. Gate array 10 also includes Vdd metal line 18 and Vss metal line 16 ringing the core perimeter to provide power and ground to the metal lines 22 and 21.
The gate array structure 10 also includes input/output ("I/O") pads 12 and I/O slots 14 located around the perimeter of the die 23 and outside of the core region 24. These pads form the contact region for wire bonds or other electrical connections that connect the IC circuitry to external elements. The I/O slots 14 contain transistors and other devices used for interfacing with the external elements to which die 23 is connected. Typically slots 14 will provide such functions as Electrostatic Discharge (ESD) protection, predrivers, and input and output buffers, etc.
One suitable base cell design for gate arrays has been developed and used by LSI Logic Corporation of Milpitas, California (assignee of the present invention). This design employs 8 MOS transistors: 4 n-type and 4 p-type, all of approximately the same size, and is illustrated in FIG. 1b. As shown, a base cell 50 (corresponding to base cell 20 in FIG. 1 a for example) is formed on a p-type substrate 64, and includes an n-type transistor side 54, and a p-type transistor side 52. The p-type transistor side 52 includes an n-well 56, in which four p-type transistors 53a-53d, all aligned in parallel with a single axis, are formed. As shown, each p-type transistor is identically sized and shaped. Some or all of these transistors will form circuits after they are wired to one another and/or other transistors by back-end processing.
Focusing on the p-type transistor 53d, a polysilicon gate electrode 67 is provided between a source diffusion region 59 and a drain diffusion region 57. Also, the gate electrode 67 terminates in two polysilicon contacts ("poly-heads") 58a and 58b. A tap 69 is provided between transistors 53b and 53c to provide contact to a Vdd power line.
The n-type transistor side 54 includes four n-type transistors 55a-55d, all aligned parallel with the transistors of p-type transistor side 52. As shown in n-type transistor 55d, for example, a gate electrode 66 of similar size and shape to gate 67 is provided. Further, a tap 68 is provided between n-type transistors 55b and 55c to provide contact to a Vss ground line.
Gate array designs as shown in FIGS. 1a and 1b should be contrasted with "cell based" designs. Cell based designs generally employ, in the chip's core region, many different base cells, as opposed to a single repeating base cell. Typically, the various base cells have different sizes, shapes, transistor arrangements, etc., and they are laid out in a manner chosen for a given integrated circuit design. Because the base cell choice and arrangement is dictated by the integrated circuit design, cell based designs generally use available chip space more efficiently than gate array designs. However, cell based technology is often unsuitable for use with ASICs which are manufactured in insufficient volume to recoup the additional development costs generally associated with the cell based design process. Thus, gate array designs will continue to find widespread use in ASIC designs.
Gate array designers face a continuing challenge of simplifying on-chip routing. To the extent that they meet this challenge they increase the chip space utilization and, at the same time, reduce the fabrication process complexity. Routing refers to the electrical connections made on ICs between individual transistors to form circuitry. Such connections are made with conductive vertical interconnects between transistors at the IC substrate level and metallization layers sitting above the substrate. Dielectric layers electrically insulate the metallization layers from one another and from the substrate. Each such metallization layer is patterned to form various metal lines that electrically link device elements from multiple transistors and thereby form the IC's circuitry. The complexity of modem gate arrays typically requires at least two and often more metallization layers. Unfortunately, each additional metallization layer adds significantly to the cost and complexity of fabricating the gate array.
Much of the routing in any gate array design functions to define the individual circuits that make up the IC. Such circuits may be simple logic gates such as NAND gates as well as more complex circuitry such as multiplexers and flip flops with multiple inputs. In addition to such basic circuit-level routing, ICs also employ a certain amount of "chip-level routing" which connects the various circuits together to form a functioning IC. Such chip-level routing is made up of metallization lines that may have to cross many base cells. To the extent that circuit-level routing occupies space on a given metallization level, that space is unavailable for chip-level routing. In fact, if the circuit-level routing occupies too much space it may be necessary to employ another metallization layer for some or all of the chip-level routing. Thus, gate array designs that reduce the amount of circuit-level routing at the first and second metallization levels can significantly reduce the cost of an IC.
For illustration purposes only, FIG. 1c shows a plurality of base cells 80 having individual base cells 82a-82d. The first metallization layer (metal-l) is not shown in order to illustrate how circuit-level routing is typically implemented a second metallization layer (metal-2). If a complex flip flop circuit, for example, is constructed on the plurality of base cells 82a-82d, the metal-1 interconnects could not in themselves completely wire the flip flop. Thus, metal-2 jumpers 84, 86, 88, 90 and 92 are required to complete the necessary transistor interconnections. Via contacts such as contacts 81a and 81b that are used to provide interlayer connections. As shown, metal-2 jumpers 84, 86, 88, 90 and 92 leave much of the room on the left and central regions of the base cells unavailable for chip-level routing. In some instances, more metallization lines must be formed from a third metallization layer (metal-3).
In view of the above example and the general need to reduce the number of steps in gate array fabrication, it would be desirable to provide a gate array masterslice that reduces the amount of circuit-level routing in the first and/or second metallization levels.